1. Field of the Invention
The present invention relates in general to a content addressable memory (referred to hereinafter as CAM) cell and a CAM cell array used in a cache memory and a variable length coder in a digital system, and more particularly to a self-refreshable dual port dynamic CAM cell having a minimized, occupied area and a dynamic CAM cell array refreshing circuit.
2. Description of the Prior Art
Generally, a CAM cell is used in a cache memory, a programmable variable length decoder and a reprogrammable programmable logic array (PLA) in a digital system. A CAM uses a dynamic memory cell to make a cell size smaller when a memory cell array size is larger. The dynamic memory cell requires a refresh operation.
A main function of the CAM is to find a match address corresponding to the memory contents, whereas a main function of a general dynamic random access memory (referred to hereinafter as DRAM) is to write and read data. It is very hard to insert a refresh cycle in the middle of performing the above functions. In the case where the refresh cycle is inserted in the middle of performing the above functions, a very complex control system is required or a system including the dynamic CAM cell is reduced in performance. The refresh operation is more frequently performed in the CAM of the dynamic type rather than the DRAM because the CAM has a much smaller storage capacity than that of the DRAM. The dynamic CAM cell can perform a self-refresh operation to have an external static operating characteristic, without requiring an external refresh operation. However, the self-refresh operation of the dynamic CAM cell has a disadvantage in that it has an effect on a data read operation. For reference, the self-refresh operation of the dynamic CAM cell will hereinafter be described with reference to FIG. 1.
Referring to FIG. 1, there is shown a circuit diagram of a conventional dynamic CAM cell. At the initial state, data are written in dynamic storage nodes a and b, and a match line 17 is precharged with a high voltage. When a match operation is performed by the CAM after the data are stored in the dynamic storage nodes a and b, a word line 15 becomes "0" in logic, thereby causing no further data to be written in the dynamic storage nodes a and b. Then, data to be compared are supplied to true and complementary bit lines 11 and 13.
In the case where the data stored in the dynamic storage nodes a and b are the same as those on the true and complementary bit lines 11 and 13, the match line 17 maintains the initially precharged high voltage. On the contrary, in the case where the data stored in the dynamic storage nodes a and b are not the same as those on the true and complementary bit lines 11 and 13, the match line 17 is discharged to "0" in logic. For example, provided that high data is supplied to the true bit line 11 and low data is supplied to the complementary bit line 13 at the initial state, low data is stored in the dynamic storage node a and high data is stored in the dynamic storage node b. If a high value is supplied to the true bit line 11 and a low value is supplied to the complementary bit line 13 during the match operation, MOS transistors Q2 and Q3 are turned off, thereby causing the match line 17 to maintain a high impedance or the initially precharged high voltage. On the contrary, if a low value is supplied to the true bit line 11 and a high value is supplied to the complementary bit line 13 during the match operation, the MOS transistor Q3 and a MOS transistor Q4 are turned on, thereby causing the match line 17 to be discharged to a low value.
In order to refresh the dynamic storage nodes a and b in FIG. 1, a refresh cycle must be inserted between the normal operations or the match operations of the CAM to turn on the word line 15 and supply address data to the true and complementary bit lines 11 and 13. In this manner, the refresh operation of the dynamic CAM cell can be accomplished.
However, the dynamic storage nodes of the dynamic CAM cell can perform a data read operation during the normal match operation. The data read operation of the dynamic CAM cell is affected by the refresh operation.